As integrated circuits (IC) have become smaller and more complex, IC designers use electronic design automation (EDA) software tools to design integrated circuits. Typically, the integrated circuit design process begins with a specification, which describes the functionality of the integrated circuit and may include a variety of performance requirements. Then, during a logic design phase, the logical implementation of the IC functionality is described using one of several hardware description languages such as Verilog or VHDL at the register transfer logic (RTL) level of abstraction. Typically, the EDA software tool synthesizes the abstract logic into a technology dependent netlist using a standard library from an IC manufacturer. The RTL can also describe the behavior of the circuits on the chip, as well as the interconnections to inputs and outputs.
After completion of the logic design phase, the IC undergoes a physical design phase. The physical design phase creates a semiconductor chip design from the RTL design and a library of available logic gates, and includes determining which logic gates to use, defining locations for the logic gates and interconnecting the logic gates. The physical design phase outputs design layouts.
After a design layout is prepared, masks for use in fabrication of the IC are generated using mask preparation tools. In advanced nodes production, such as 10 nm nodes and 5 nm nodes, layout designs may include features distributed in irregular regions to satisfy complicated functionality. For example, fin features can be formed in a donut shaped region. It takes a long time to generate masks for layout designs in advanced nodes production using traditional mask generating methods. Sometimes, pattern features may be missed from the mask pattern.